Analyze Massive Data Graphs On Your PC With This Device
We like our computers to be general-purpose, but specialty hardware has been creeping in since the beginning. Remember when Intel introduced the 287 math coprocessor, a dedicated chip that only did math? It was faster, more efficient, and allowed logic operations to be done concurrently. Today, lots of high-level functionality is done in auxiliary devices. Here’s a cool new device dedicated solely to sort/reduce massive data graphs: Fast, cheap, and uses far less power.
Everyone is aware of the mounting problem we’re having with the astronomical power consumption of our new High-Performance Computing (HPC). All of the astonishing machine learning were doing these days continually spotlights the situation. In fact power consumption is so great that the heat dissipation is a major consideration for locating new computational centers. Google tries to build them next to rivers just to take advantage of the water as a heat sink. Microsoft is building HPC computer arrays that are sealed in watertight containers and placed on the sea floor (where the water is very cold). These are obviously extreme solutions.Researchers at MIT CSAIL Found a smarter way to do Graph Analysis algorithms in dedicated hardware. We’re all familiar with the Nvidia GPGPUs, and Google has devised its specialized hardware to do tensor (matrix) manipulations called Tensor Processing Units (TPUs).
The CSAIL researchers tackled the problem of analyzing graphs. Conceptually, graphs are just a collection of nodes with connections drawn as lines between them (mathematicians call them “edges”). Visualize a large website. Imagine each page as a node and all of the links to other pages as lines drawn between the nodes. It can be a very large graph, but lots of other things are huge graphs:
In order for it to be practical to navigate through such graphs, examining nodes of interest and exploring where they lead the graph must be in computer RAM. Why in RAM? The connections between nodes are simply memory pointers to other nodes. While the graph seems structured as a concept, it is actually implemented as random jumps all over the data space. Linked nodes are rarely near each other in memory. The graphs we manipulate today consist of billions of nodes and many billions of connections between those nodes. So, it’s not surprising that machines used for graph manipulation typically have 128 GB of DRAM. Even at today’s memory prices, that much memory is expensive. However, even with all that memory available, there is the power issue. Power usage goes up as a direct function of memory access. Viewing data at a specific location and/or altering that data is a direct determinant of how much power is consumed, and when one is ferociously traversing the graph, most of the work being done is memory access as opposed to CPU computation. When the graph gets larger than a single computer can hold, then the problems become worse because data must be shuttled between servers, which is orders of magnitude more power-hungry (and slower).
Initial attempts to combat the power-hungry DRAM were to replace it with flash memory. Flash uses much less power and is physically much smaller, but in a random access application, it is orders of magnitude slower (flash memory access speeds are somewhere between hard drives and RAM). Something more was needed, and in this case, they added searching algorithm special sauce. The idea was to sort the incoming stream of graph node address requests into something resembling more efficient walks through the tree picking up nodes as they went. Then, of course, the resulting nodes had to be merged with their original node address requests. Essentially, the hardware device implements a complete sort merge process using a small amount of DRAM and a large amount of flash RAM; but more on this a little later.
The research team tested their system against traditional hardware using the Web Data Commons Hyperlink Graph (3.
